verilog representation of a flops -

i teaching myself verilog , trying write modelling flop. have come across following modeling ck->q delay arcs in specify section not understand dos.

(posedge ck => (q : 1'b1))=(0, 0);

can explain me on how works? when d=1, ck->q considers these delays? if need have (posedge ck => (q : 1'b0))=(0, 0);

then x propagation on pin d

verliog can used model many levels. simple behavioural model, rtl (synthesizable) modelling transfer of data , control or gate level @ logic gate level, (ands ors, flip-flops). typically gate level has aware of these delays.

the typical way of modelling flip-flip behaviour in rtl :

always @(posedge clk) begin   q <= d; end