debugging - verilog always block within a initial block not proper syntax? -


i keep getting weird syntax errors, wondering if knows why getting these errors. read can't have block within initial block, when try move block outside initial block still error.

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update: problem solved. although, moved block outside of initial block, , stopped receiving syntax errors. answer provided why blocks not allowed in... enter image description here

two syntax rules:

  • repeat blocks must within initial blocks
  • always blocks must outside initial blocks.

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