VHDL test bench error please help, for school (SOLVED) -

im trying make test bench program, says "physical unit hidden declaration of 'w' @ line 6." it's project school, , cant find out why doesn't work.. thanks!

the program:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity comp generic (w : natural  );   port (a_v     :in  std_logic_vector((w-1) downto 0); --vector aan ingang       b_v     :in  std_logic_vector((w-1) downto 0); --vector b aan ingang             groter   :out std_logic;  --led 'groter' actief indien a>b             gelijk   :out std_logic);  --led 'gelijk' actief indien a==b end comp;  architecture behavior of comp  --signal ci1, ci2: std_logic; begin proc: process (a_v,b_v) begin  if (a_v=b_v) groter<='0'; gelijk<='1';  elsif (a_v>b_v) groter<='1'; gelijk<='0';  else groter<='0'; gelijk<='0'; end if;   end process proc;  end behavior; 

---

the test bench:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity comp_test generic (w : natural := 5);   end comp_test;  architecture structural of comp_test   -- unit under test: uut     component comp  generic (w : natural);  port (a_v     :in  std_logic_vector(w-1 downto 0); --vector aan ingang       b_v     :in  std_logic_vector(w-1 downto 0); --vector b aan ingang             groter   :out std_logic;  --led 'groter' actief indien a>b             gelijk   :out std_logic);  --led 'gelijk' actief indien a==b      end component;    uut: comp use entity work.comp(behavior);      constant period : time := 100 ns;   signal   end_of_sim : boolean := false;  -- naturalerconnection (signals - ports) signal a_v     :  std_logic_vector(w-1 downto 0); --vector aan ingang signal b_v     :std_logic_vector(w-1 downto 0); --vector b aan ingang signal  groter   : std_logic;  --led 'groter' actief indien a>b signal  gelijk   : std_logic;  --led 'gelijk' actief indien a==b  begin      uut : comp      generic map (w=>5 )     port map(         a_v   => a_v,         b_v   => b_v,         groter => groter,         gelijk => gelijk      );  -- test bench: tvi-generator    tb_gen : process   variable i_v: std_logic_vector((2w-1) downto 0);    begin    in 0 (2**2w-1)   loop     a_v<=i_v(2w-1 downto w);   b_v<=i_v(w-1 downto 0);     i_v:=i_v+1;     wait period;   end loop;   end_of_sim <= true;   wait;   end process tb_gen; end structural; 

i warn ... you'll kick yourself!

variable i_v: std_logic_vector((2w-1) downto 0);

the error message telling physical quantity comprising value , physical unit (like 2 ns, 2 ms, or ... 2 w), cannot parsed because declaration of w hides alleged physical unit!

if there no declaration of w see different error (no declaration of such physical unit - mw w kw etc legally declared, represent power, same way ns etc pre-declared represent time.)

whereas ...

you aiming multiply w 2 ... in

variable i_v: std_logic_vector((2*w - 1) downto 0);