caching - Understanding caches and block sizes -

a quick question make sure understand concept behind "block" , usage caches.

if have small cache holds 4 blocks of 4 words each. let's directly mapped. if try access word @ memory address 2, block contains words 0-3 brought first block position of cache or bring in words 2-5 instead?

i guess question how "blocks" exist in memory. when value accessed , cache miss trigger, cpu load 1 block's worth of data (4 words) starting @ accessed value in memory or calculate block word in memory in , brings block instead.

if question hard understand, can provide diagrams i'm trying explain.

usually caches organized "cache lines" (or, put it, blocks). contents of cache need associatively addressed, ie, accessed using portion of requested address (ie "lookup table key" if will). if cache uses block size of 1 word, entire address -- n bits of -- "key". each word accessible granularity described.

however, associative key matching process hardware intensive, , bottleneck in both design complexity (gates used) , speed (if want use fewer gates, take speed hit in tradeoff). certainly, @ point, cannot minimize gate usage trading off speed (delay in accessing desired element), because cache's whole purpose fast!

so, tradeoff done little differently. cache organized blocks (cache "lines" or "rows"). each block starts @ 2^n aligned boundary corresponding cache line size. example, cache line of 128 bytes, cache line key address have 0's in bottom 7 bits (2^7 = 128). eliminates 7 bits address match complexity mentioned earlier. on other hand, cache read entire cache line cache memory whenever part of cache line "needed" due "cache miss" -- address "key" not found in associative memory.

now, seems like, if needed byte 126 in 128-byte cache line, you'd twiddling thumbs quite while, waiting cache block read in. accomodate situation, cache fill can take place starting "critical cache address" -- word processor needs complete current fetch cycle. allows cpu go on merry way quickly, while cache control unit proceeds onward -- reading data word word in modulo n fashion (where n cache line size) cache memory.

the old mpc5200 powerpc data book gives pretty description of kind of critical word cache fill ordering. i'm sure it's used elsewhere well.

hth... jogusto.