JK flipflop code in verilog using structural -

i writing verilog program jk flipflop in structural level program follows:

module jkstruct(j,k,clk,q,qbar);  input j,k,clk;  output reg q,qbar;  initial begin q=1'b1;qbar=1'b0; end  wire x,y,w,z;  assign w=q;  assign z=qbar;  nand n1(x,z,j,clk);  nand n2(y,k,w,clk);  nand n3(q,x,z);  nand n4(qbar,y,w);  endmodule 

erroor:simulator:754 - signal exception_access_violation receivedprinting stacktrace...

was appearing on simulator error panel. using xilinx 13.4 licensed version.

you initialising outputs

initial begin q=1'b1;qbar=1'b0; end 

when combinatorially driven :

nand n3(q,x,z); nand n4(qbar,y,w); 

the above requires output connected via wire not reg.

remove initial, , reg declaration (apply change below), , report if issue still persists.

output q,qbar; // output reg q,qbar;